6. January 2010, 22:41:40
US Patent 6944746 - RISC processor supporting one or more uninterruptible co-processors
1. A method of processing instructions in a computer system comprising a processor
and a co-processor communicatively coupled to the processor, wherein the processor includes a co-processor interface communicatively coupled to the co-processor, the method comprising:

(a) processing instructions in the processor in an instruction pipeline wherein instructions are processed sequentially by an instruction fetch stage, an instruction decode stage, an instruction execute stage, a memory access stage and a result write-back stage; and

(b) if a co-processor instruction is received by the processor, performing steps of:

(b)(i) providing the co-processor instruction to the co-processor interface during the instruction execute stage: and (b)(ii) transmitting the co-processor instruction from the co-processor interface to the co-processor during the memory access stage.

2. The method of claim 1 further comprising a step (c) of:

(c) if an interrupt or exception is received by the processor, canceling an instruction that is in the instruction execute stage when the interrupt is received and reissuing the instruction starting at the instruction fetch stage.

3. The method of claim 2 wherein if an interrupt or exception is received by the processor when a co-processor instruction is in the instruction execute stage, the co-processor instruction is canceled before the co-processor instruction is transmitted to the co-processor and the co-processor instruction is reissued starting at the instruction fetch stage.

4. The method of claim 1 wherein the co-processor is a processing element for which sending the same co-processor instruction to the co-processor twice decreases the performance of the co-processor.

5. The method of claim 1 wherein the processor is a reduced instruction set computer (RISC) processor.


6. The method of claim 1 wherein the system is a media decoding system, the processor is a core decoder processor and the co-processor is a decoding accelerator adapted to assist the core processor with a decoding function.

7. A computer system comprising:

a processor adapted to process instructions in an instruction pipeline wherein instructions are processed sequentially by an instruction fetch stage, an instruction decode stage, an instruction execute stage, a memory access stage and a result write-back stage, the processor including a co-processor interface; and

a co-processor communicatively coupled to the co-processor interface of the processor and adapted to perform processing tasks in response to co-processor instructions provided by the processor;

wherein the processor is adapted to provide a co-processor instruction to the co-processor interface during the instruction execute stage and wherein the co-processor interface is adapted to transmit the co-processor instruction to the co-processor during the memory access stage.

8. The system of claim 7 wherein if an interrupt is received by the processor, the processor is adapted to cancel an instruction that is in the instruction execute stage when the interrupt is received and to reissue the instruction starting at the instruction fetch stage.

9. The system of claim 8 wherein if an interrupt is received by the processor when a co-processor instruction is in the instruction execute stage, the processor is adapted to cancel the co-processor instruction before the co-processor instruction is transmitted to the co-processor and to reissue the co-processor instruction starting at the instruction fetch stage.

10. The system of 7 wherein the co-processor is a processing element for which sending the same co-processor instruction to the co-processor twice decreases the performance of the co-processor.

11. The system of claim 7 wherein the processor is a reduced instruction set computer (RISC) processor.

12. The system of claim 7 wherein the system is a media decoding system, the processor is a core decoder processor and the co-processor is a decoding accelerator adapted to assist the core processor with a decoding function.
Other References

* U.S. Appl. No. 09/437,208 entitled “Graphics Display System”, filed Nov. 9, 1999, Inventor: Alexander G. Macinnis et al.
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Inventor

* So, Kimming

Application
No. 10113094 filed on 04/01/2002

US Classes:
712/34, Including coprocessor712/244, Exeception processing (e.g., interrupts and traps)710/260, INTERRUPT PROCESSING345/519Integrated circuit (e.g., single chip semiconductor device)

Field of Search
712/34, Including coprocessor712/35, Digital Signal processor712/244, Exeception processing (e.g., interrupts and traps)710/268, Source or destination identifier710/267, Processor status710/265, Variable710/266, Programmable interrupt processing710/260, INTERRUPT PROCESSING710/262, Interrupt inhibiting or masking710/264, Interrupt prioritizing710/269, Handling vector710/263, Interrupt queuing710/261Multimode interrupt processing

Examiners
Primary: Treat, William M.

Attorney, Agent or Firm

* McAndrews, Held & Malloy, Ltd.

US Patent References
5887160, Method and apparatus for communicating integer and floating point data over a shared data path in a single instruction pipeline processor
Issued on: 03/23/1999
Inventor: Lauritzen, et al.6538656Video and graphics system with a data transport processor
Issued on: 03/25/2003
Inventor: Cheung, et al.

Foreign Patent References

* 0 793 168 EP 09/01/1997

International Class
G06F01